This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-186546, filed Jun. 30, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device and a method of manufacturing thereof.
FIGS. 12A-12C are drawings used for describing a process for manufacturing a conventional trench-MOS (Metal Oxide Semiconductor) gate structure. FIGS. 12A and 12B are cross-sectional views of a device of the trench-MOS gate structure in its manufacturing process, and FIG. 12C is a perspective view of the device.
In the conventional method of manufacturing, as shown in FIG. 12A, a p-type base layer 2 is formed by diffusion in a surface portion of an n-type high-resistance substrate 1, and then an n-type source layer 3 is selectively formed by diffusion in a surface portion of the p-type base layer 2. Thereafter, a trench for a MOS gate, which penetrates the n-type source layer 3 and the p-type base layer 2 and communicates with the n-type high-resistance substrate 1, is formed, and the entire surface of the substrate 1 including the trench is covered with a gate insulating film 4 (FIG. 12A). Thereafter, a gate electrode 5 is buried in the trench, and then an insulating film 6 is deposited to cover the gate electrode 5 (FIG. 12A). Thereafter, as shown in FIG. 12B, a contact window is formed and then, as shown in FIG. 12C, a MOS gate structure is formed by forming an emitter electrode 10 on the surface of the substrate 1. In the process of manufacturing the trench-MOS gate structure, a margin for mask alignment was required as shown in FIG. 12A, so that the emitter electrode 10 and the p-type base layer 2 are connected. Further, as shown in FIG. 12B, it was necessary to provide a margin for mask alignment in order to prevent short circuit between the gate electrode 5 and the emitter electrode 10. Since there were these alignment margins, scale down of the device was difficult, and property improvement such as reduction of the on-state resistance was difficult.
As described above, in a process of manufacturing a semiconductor device having a conventional trench gate structure, it was necessary to provide margins for aligning masks for formation of trench, n-type source layer and contact window. Therefore, there was the problem that scale down of the device structure was restricted by the margins for mask alignment.
The present invention has been made in consideration of such circumstances, and has its object to provide a semiconductor device and a method of manufacturing thereof, which enables scale down of a device structure.
Therefore, in order to solve the above problem, the present invention is characterized in that mask alignment is unnecessary, scale down is possible and device property is improved by alternately forming trenches and source layers for contact in a region between parallel trench gates.
Specifically, according to a first aspect of the present invention, there is provided a semiconductor device comprising:
a first conductivity-type base layer;
a second conductivity-type base layer formed on the first conductivity-type base layer;
a first conductivity-type source layer formed on the second conductivity-type base layer;
a plurality of first trenches formed in parallel to each other, which penetrate from a surface of the first conductivity-type source layer through the first conductivity-type source layer and the second conductivity-type base layer and reach the first conductivity-type base layer;
gate insulating films formed on wall surfaces of the first trenches;
gate electrodes formed within the first trenches and on the second conductivity-type base layer via the gate insulating films;
a plurality of second trenches which penetrate from the surface of the first conductivity-type source layer through the first conductivity-type source layer and reach the second conductivity-type base layer; and
a first main electrode formed within the second trenches and electrically connected to the first conductivity-type source layer and the second conductivity-type base layer,
wherein portions of the second trenches and portions of the first conductivity-type source layer are alternately arranged in regions among the first trenches.
In the semiconductor device according to the first aspect of the present invention, the semiconductor device may further comprise second conductivity-type contact layers formed in surface portions of the second conductivity-type base layer defining the second trenches, the second conductivity-type contact layers having an impurity concentration higher than the second conductivity-type base layer.
In the semiconductor device according to the first aspect of the present invention, the semiconductor device may further comprise second conductivity-type contact layers formed in surface portions of the second conductivity-type base layer defining the second trenches and second conductivity-type block layers formed in surface portions of the first conductivity-type source layer, the second conductivity-type contact layers and the second conductivity-type block layers having an impurity concentration higher than the second conductivity-type base layer.
According to a second aspect of the present invention, there is provided a semiconductor device comprising:
a first conductivity-type base layer;
a second conductivity-type base layer formed on the first conductivity-type base layer;
a first conductivity-type source layer formed on the second conductivity-type base layer;
a plurality of first trenches formed in parallel to each other, which penetrate from a surface of the first conductivity-type source layer through the first conductivity-type source layer and the second conductivity-type base layer and reach the first conductivity-type base layer;
gate insulating films formed on wall surfaces of the first trenches;
gate electrodes formed within the first trenches and on the second conductivity-type base layer via the gate insulating films;
a plurality of second trenches which penetrate from the surface of the first conductivity-type source layer through the first conductivity-type source layer and reach the second conductivity-type base layer;
a first main electrode formed within the second trenches and electrically connected to the first conductivity-type source layer and the second conductivity-type base layer;
a high impurity concentration base layer and a second conductivity-type collector layer superposed on a surface of the first conductivity-type base layer, which surface is opposed to a surface thereof on which the second conductivity-type base layer is formed, the high impurity concentration base layer having an impurity concentration higher than the first conductivity-type base layer and being of the first conductivity-type; and
a second main electrode formed on the second conductivity-type collector layer,
wherein portions of the second trenches and portions of the first conductivity-type source layer are alternately arranged in regions among the first trenches.
In the semiconductor device according to the second aspect of the present invention, the semiconductor device may further comprise second conductivity-type contact layers formed in surface portions of the second conductivity-type base layer defining the second trenches, the second conductivity-type contact layers having an impurity concentration higher than the second conductivity-type base layer.
In the semiconductor device according to the second aspect of the present invention, the semiconductor device may further comprise second conductivity-type contact layers formed in surface portions of the second conductivity-type base layer defining the second trenches and second conductivity-type block layers formed in surface portions of the first conductivity-type source layer, the second conductivity-type contact layers and the second conductivity-type block layers having an impurity concentration higher than the second conductivity-type base layer.
According to a third aspect of the present invention, there is provided a semiconductor device comprising:
a first conductivity-type base layer;
a second conductivity-type base layer formed on the first conductivity-type base layer;
a first conductivity-type source layer formed on the second conductivity-type base layer;
a plurality of first trenches formed in parallel to each other, which penetrate from a surface of the first conductivity-type source layer through the first conductivity-type source layer and the second conductivity-type base layer and reach the first conductivity-type base layer;
gate insulating films formed on wall surfaces of the first trenches;
gate electrodes formed within the first trenches and on the second conductivity-type base layer via the gate insulating films;
a plurality of second trenches which penetrate from the surface of the first conductivity-type source layer through the first conductivity-type source layer and reach the second conductivity-type base layer;
a first main electrode formed within the second trenches and electrically connected to the first conductivity-type source layer and the second conductivity-type base layer,
a drain layer formed on a surface of the first conductivity-type base layer, which surface is opposed to a surface thereof on which the second conductivity-type base layer is formed, the drain layer having an impurity concentration higher than the first conductivity-type base layer and being of the first conductivity-type; and
a second main electrode formed on the drain layer,
wherein portions of the second trenches and portions of the first conductivity-type source layer are alternately arranged in regions among the first trenches.
In the semiconductor device according to the third aspect of the present invention, the semiconductor device may further comprise second conductivity-type contact layers formed in surface portions of the second conductivity-type base layer defining the second trenches, the second conductivity-type contact layers having an impurity concentration higher than the second conductivity-type base layer.
In the semiconductor device according to the third aspect of the present invention, the semiconductor device may further comprise second conductivity-type contact layers formed in surface portions of the second conductivity-type base layer defining the second trenches and second conductivity-type block layers formed in surface portions of the first conductivity-type source layer, the second conductivity-type contact layers and the second conductivity-type block layers having an impurity concentration higher than the second conductivity-type base layer.
According to a fourth aspect of the present invention, there is provided a semiconductor device comprising:
a first conductivity-type base layer;
a second conductivity-type base layer formed on the first conductivity-type base layer;
a first conductivity-type source layer formed on the second conductivity-type base layer;
a plurality of first trenches formed in parallel to each other, which penetrate from a surface of the first conductivity-type source layer through the first conductivity-type source layer and the second conductivity-type base layer and reach the first conductivity-type base layer;
gate insulating films formed on wall surfaces of the first trenches;
gate electrodes formed within the first trenches and on the second conductivity-type base layer via the gate insulating films;
a plurality of second trenches which penetrate from the surface of the first conductivity-type source layer through the first conductivity-type source layer and reach the second conductivity-type base layer;
a first main electrode formed within the second trenches and electrically connected to the first conductivity-type source layer and the second conductivity-type base layer;
a high impurity concentration base layer formed on the first conductivity-type base layer, the high impurity concentration base layer being separated from the second conductivity-type base layer, the high impurity concentration base layer having an impurity concentration higher than the first conductivity-type base layer and being of the first conductivity-type;
a second conductivity-type collector layer formed on the high impurity concentration base layer; and
a second main electrode formed on the second conductivity-type collector layer,
wherein portions of the second trenches and portions of the first conductivity-type source layer are alternately arranged in regions among the first trenches.
In the semiconductor device according to the fourth aspect of the present invention, the semiconductor device may further comprise second conductivity-type contact layers formed in surface portions of the second conductivity-type base layer defining the second trenches, the second conductivity-type contact layers having an impurity concentration higher than the second conductivity-type base layer.
In the semiconductor device according to the fourth aspect of the present invention, the semiconductor device may further comprise second conductivity-type contact layers formed in surface portions of the second conductivity-type base layer defining the second trenches and second conductivity-type block layers formed in surface portions of the first conductivity-type source layer, the second conductivity-type contact layers and the second conductivity-type block layers having an impurity concentration higher than the second conductivity-type base layer.
According to a fifth aspect of the present invention, there is provided a semiconductor device comprising:
a first conductivity-type base layer;
a second conductivity-type base layer formed on the first conductivity-type base layer;
a first conductivity-type source layer formed on the second conductivity-type base layer;
a plurality of first trenches formed in parallel to each other, which penetrate from a surface of the first conductivity-type source layer through the first conductivity-type source layer and the second conductivity-type base layer and reach the first conductivity-type base layer;
gate insulating films formed on wall surfaces of the first trenches;
gate electrodes formed within the first trenches and on the second conductivity-type base layer via the gate insulating films;
a plurality of second trenches which penetrate from the surface of the first conductivity-type source layer through the first conductivity-type source layer and reach the second conductivity-type base layer;
a first main electrode formed within the second trenches and electrically connected to the first conductivity-type source layer and the second conductivity-type base layer;
a drain layer formed on the first conductivity-type base layer, the drain layer being separated from the second conductivity-type base layer, the drain layer having an impurity concentration higher than the first conductivity-type base layer and being of the first conductivity-type; and
a second main electrode formed on the drain layer,
wherein portions of the second trenches and portions of the first conductivity-type source layer are alternately arranged in regions among the first trenches.
In the semiconductor device according to the fifth aspect of the present invention, the semiconductor device may further comprise second conductivity-type contact layers formed in surface portions of the second conductivity-type base layer defining the second trenches, the second conductivity-type contact layers having an impurity concentration higher than the second conductivity-type base layer.
In the semiconductor device according to the fifth aspect of the present invention, the semiconductor device may further comprise second conductivity-type contact layers formed in surface portions of the second conductivity-type base layer defining the second trenches and second conductivity-type block layers formed in surface portions of the first conductivity-type source layer, the second conductivity-type contact layers and the second conductivity-type block layers having an impurity concentration higher than the second conductivity-type base layer.
According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
forming a plurality of first trenches for gates in parallel to each other on a semiconductor substrate;
forming gate insulating films within the first trenches;
forming gate electrodes within the first trenches and on the gate insulating films;
forming an interlayer insulating film on an entire surface of the semiconductor substrate including the gate electrodes;
removing a portion of the interlayer insulating film, which is on the semiconductor substrate, with portions of the interlayer insulating film on the gate electrodes being left; and
forming a plurality of second trenches for contact, with the left portions of the interlayer insulating film and resist patterns used as masks,
wherein the second trenches are formed at a predetermined interval at surface regions of the semiconductor substrate, which are located between the first trenches.
In the method of manufacturing a semiconductor device, according to the sixth aspect of the present invention, the manufacturing method may further comprise the step performed succeeding to the step of forming the plurality of second trenches for contact, of performing an impurity implantation to form second conductivity-type contact layers in surface portions of the second conductivity-type base layer defining the second trenches, the second conductivity-type contact layers having an impurity concentration higher than the second conductivity-type base layer.
In the method of manufacturing a semiconductor device, according to the sixth aspect of the present invention, the manufacturing method may further comprise the step performed succeeding to the step of forming the plurality of second trenches for contact, of removing the resist patterns, and the step performed succeeding to the step of removing the resist patterns, of performing an impurity implantation to form second conductivity-type contact layers in surface portions of the second conductivity-type base layer defining the second trenches and second conductivity-type block layers formed in surface portions of the first conductivity-type source layer, the second conductivity-type contact layers and the second conductivity-type block layers having an impurity concentration higher than the second conductivity-type base layer.
According to the present invention, since a trench-MOS gate structure can be formed without mask alignment, scale down of the device is possible and the device property is improved.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.